1. Field of the Invention
This invention relates to the field of memory systems for use in data processing systems. More particularly, it relates to an improvement in memory systems that store data words at addressable locations in conjunction with error correction code signals, the improved memory system including through checking circuitry for checking the integrity of the recorded data words and the encoding and decoding of the associated error correction code signals.
2. Description of the Prior Art
Memory systems of various types have been developed through the years for use with data processing systems. These memory systems have included systems that store data serially, such as on magnetic, tapes, and those systems that store data at addressable locations. The latter type of systems are often referred to as "random access" systems indicating that the data is capable of being specifically identified and retrieved. Such access is in fact not "random", but instead, may more properly be referred to as "arbitrary access". Addressable memories can include various types of structures that are well known. These include magnetic drums, magnetic disks, magnetic core memories, integrated circuit memories, as well as other more esoteric memory configurations. Common to all memory systems utilized in binary data processing systems is the ability to record and read back some form of manifestation that can be distinguished between two possible states; one state indicating a binary zero and the other state indicating an binary one.
It has long been recognized that the integrity of the data bits stored and retrieved is critical to the accuracy of calculations performed in the data processing system. The alteration of one bit in a data word could dramatically affect arithemtic calculations, or could change the meaning of the recorded data. It was recognized that by associating an additional bit, called a "parity bit", with the binary bits comprising an addressable word, that erroneous data words could be detected. Parity is well known, and simply involves summing without carry the one bits in a data word and providing an additional parity bit that renders the total count across the data word including the parity bit either odd or even. It was determined that a single parity bit in conjunction with a data word comprised of multiple bits, for example 36-bits, that multiple error would defeat the parity system. As calculation rates increase, circuit sizes decrease, and signal levels correspondingly were reduced, the likelihood of errors occurring increased.
It had been recognized in data transmission systems that by properly encoding data bits, multiple errors could be detected and corrected after transmission. The overhead for such additional accuracy was the necessity for transmitting a larger number of bits since the error detection/correction signals had to be transmitted along with the data bits. The efficacy of utilization of error correction code signals was recognized for use in memory systems, and prior art systems have been developed wherein the data word to be stored in an addressable memory location is encoded to provide error correction code (ECC) signals that are stored along with the bits of the data word. Upon readout, the data bits read from the addressable memory location are again subjected to the generation of the same error correction code signal pattern, and the newly generated pattern is compared to the error correction code signals stored in the memory. If a difference is detected, it is determined that the data word is in error. Depending upon the encoding system utilized it is possible to identify and correct the bit position in the data word indicated as being incorrect. The system overhead for the utilization of error correction code signals is the time necessary to generate them, the memory cells necessary to store them, and the time required to make the decode at readout. These are the offsetting disadvantages for the advantageous operation involving data recording and reading back that has a higher degree of accuracy and integrity than systems that do not utilize the error correction code system.
With the addition of the circuitry necessary to generate the error correction code signals and the additional memory cells necessary to store them, it has been recognized that errors can occur in the generation of the error correction code signals through circuit faults, through the erronneous recording or readback of the error correction code signals through memory cell failure, or through read/write circuit failure. Such failures would lead to the indication of erronneous data, with the possibility of correct data bits being altered in the correction system, when in fact the error occured in the error correction code signal handling.
Systems have been developed utilizing redundant circuitry for performing various integrity checking functions, with the attendant additional cost of hardware, together with its own error-inducing probability due to circuit malfunction.
An example of a system that decribes generation of error correction code signals and the readout thereof, is in co-pending U.S. patent application entitled, "Memory Driver Failure Detection System and Method", Gary David Burns and Ferris Thomas Price the inventors, Ser. No. 324,290, now abandoned and assigned to the assignee of this invention. An example of a system that functions to check the accuracy of generation of error correction code signals prior to recording is described in co-pending U.S. patent application entitled, "Error Correction Code Through Check System", John Reed Trost the inventor, Ser. No. 354,328, and assigned to assignee of this invention. Each of the referrenced co-pending patent applications is directed at maintaining the integrity of data through the memory system, and are particularly useful in identifying the causes of detected malfunctions, but do not directly provide for through checking of the error correction codes wherein malfunctions of circuitry on readout are detected.